Manufacturers of chips that contain integrated circuits ("ICs") may use a chip burn-in testing procedure to detect latent failures which may occur in the IC. The purpose of burn-in testing is to detect certain fabrication defects in a chip that may not be manifested outright as a chip failure. These defects may only appear sometime after the chip has power applied and the inputs and outputs ("I/Os") of the chip are exercised. Thereafter, the stress of operation may cause these defects to be manifested. These latent failures may be more difficult to isolate after the chip is integrated into a system due to inaccessibility of the I/O connections of the chip at the system level. By conducting a chip level burn-in testing procedure, these latent failures may be weeded out prior to integrating the chip into a system.
Chip burn-in testing is conducted by subjecting a chip to operating stresses, prior to integrating the chip into a system. In the case where the chip is prone to a latent failure, the stress of burn-in often times causes the latent failure to be manifested. Burn-in testing is typically conducted at temperatures in excess of 100.degree. C. and for prolonged periods of time(e.g., 40-80 hours) with the chip running at operating voltages. In the prior art, the burn-in testing procedure may only be practically conducted on a chip that is individually packaged in one of the standard formats. In this way, the chip may be plugged into a standard burn-in testing system for burn-in testing.
Currently, it is more and more common for chips not to be packaged. For unpackaged chips, the current methods of conducting burn-in testing greatly increase the cost of producing the chip. Yet, burn-in testing is equally important for an unpackaged chip as it is for a packaged chip.
The need for burn-in testing may be readily illustrated with reference to a typical application for bare (e.g., unpackaged) chips. As an example, eight bare chips may be utilized for flip-chip assembly onto a printed circuit board ("PCB") for making a single in-line memory module ("SIMM") card. For a given wafer type and fabrication process, a dropout rate (e.g., failure rate) of 3% during burn-in may be typical.
For a case when no burn-in test is conducted, the chips will fail some time after integration into the SIMM card. For a premature failure probability of 0.03 per chip (see above), the premature failure probability of the SIMM module comprising eight chips is 0.22. This means that roughly one out of five SIMM modules will fail prematurely. This is an unacceptably high number of PCB failures for a production environment.
Burn-in testing prior to assembly (chip integration into a system) is desirable since it reduces rework (e.g., removal of bad chips) at the system level. Preferably, burn-in testing for any applications involving bare chips should be conducted prior to the chips integration into a system such as a SIMM module to reduce rework at the module level. Therefore, a practical method of detecting the burn-in failures should be conducted upstream of the production process prior to a chip's integration into a system (e.g., a SIMM module).
There are several prior art methods for conducting a bare chip burn-in procedure. In one prior art method, specialized test sockets are fabricated to house a chip for bare chip burn-in testing. The problem with this method is that it is very expensive and may result in chip costs that are two to four times the cost of the original chip. Still another prior art method of conducting bare chip testing entails placing the chip in a chip-carrier. The chip-carrier acts as a temporary packaging. The temporary packaging is configured to fit into in an existing burn-in testing system. This method is also very expensive and again may result in chip costs that are two to four times the cost of the original packaged chip.
In another prior art method, the chip may be tested prior to separation from a wafer on which the chip is fabricated. In this method, individual probes are held onto the chip I/O pads to enable burn-in testing of the chip. This method of testing a chip is not practical in a production environment since during burn-in testing, the external probes are required to be held in place for extended periods of time (e.g., 40-80 hours). Additionally, since there may typically be many individual chips on each wafer, it is a problem to position the required probes for testing all the chips on the wafer at the same time and an unacceptable period of time is required to burn-in test each chip individually.
Another problem with wafer level burn-in testing is handling all the inputs and outputs ("I/Os") required to do burn-in testing on a wafer scale. For instance, a typical eight inch memory wafer has three hundred individual chips. Each individual chip may have about thirty I/Os. For a typical burn-in procedure, only about five of the I/Os for each chip may be required. Consequently, the wafer may have a total of 1500 I/Os which may need to be driven for burn-in testing. Most prior art methods are not suitable to access all the required I/Os for wafer level burn-in testing in a production environment.
In a known-good-die test, a membrane type of supplemental wafer is aligned with, and placed on top of a wafer that is going to be tested. In this method, contacts on the supplemental wafer make contact with the I/Os of the wafer under test to enable burn-in testing. The problem with this method of testing is that the supplemental wafer is required to test the wafer under test. Consequently, for this testing process to work, a known good supplemental wafer is required to test the wafer under test. Otherwise, there is an uncertainty if a failure occurs during testing since the failure may be due to the supplemental wafer or the wafer under test.
To solve the above problems, a novel burn-in process is hereby disclosed.
Therefore, it is an object of the present invention to provide a method of conducting burn-in testing at the wafer level.
Another object of the present invention is to provide a practical method for accessing all the inputs and outputs that may be required for burn-in testing at the wafer level without requiring a supplemental wafer.
A further object of the present invention is to provide a method of wafer level burn-in testing that is cost effective.
A still further object of the present invention is to provide a method of wafer level burn-in testing that may be conducted practically in a production environment.